preliminary rev. 0.4 5/06 copyright ? 2006 by silicon laboratories si534 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si534 c rystal o scillator (xo) (10 mh z to 1.4 gh z ) features applications description the si534 quad frequency xo utilizes silicon laboratories? advanced dspll ? circuitry to provide a low jitter clock at high frequencies. the si534 is available with any-rate output frequency from 10 to 945 mhz and select frequencies to 1400 mhz. unlike a traditional xo where a different crystal is required for each output frequency, the si534 uses one fixed crystal to provide a wide range of output frequencies. this ic based approach allows the crystal resonator to provide exceptional frequency stability and reliability. in addition, dspll clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. the si534 ic-based xo is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. functional block diagram available with any-rate output frequencies from 10 mhz to 945 mhz and select frequencies to 1.4 ghz four selectable output frequencies 3rd generation dspll ? with superior jitter performance 3x better frequency stability than saw-based oscillators internal fixed crystal frequency ensures high reliability and low aging available cmos, lvpecl, lvds, and cml outputs 3.3, 2.5, and 1.8 v supply options industry-standard 5 x 7 mm package and pinout pb-free/rohs-compliant sonet/sdh networking sd/hd video clock and data recovery fpga/asic clock generation fixed frequency xo any-rate 10?1400 mhz dspll ? clock synthesis v dd clk+ clk? oe gnd fs[1] fs[0] ordering information: see page 6. pin assignments: see page 5. (top view) si5602 (lvds/lvpecl/cml) (cmos) 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc fs[1] fs[0] 7 8 1 2 3 6 5 4 gnd oe v dd clk nc nc fs[1] fs[0] 7 8 p reliminary d ata s heet
si534 2 preliminary rev. 0.4 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max units supply voltage 1 v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 1.8 v option 1.71 1.8 1.89 supply current i dd output enabled ? 90 ? ma tristate mode ? 60 ? output enable (oe) 2 v ih 0.75 x v dd ?? v v il ??0.5 operating temperature range t a ?40 ? 85 oc notes: 1. selectable parameter specified by part number. see section 3. "ordering information" on page 6 for further details. 2. oe pin includes a 17 k ? pullup resistor to v dd . pulling oe to ground causes outputs to tristate. table 2. clk output frequency characteristics parameter symbol test condition min typ max units nominal frequency 1,2 f o lvpecl/lvds/cml 10 ? 945 mhz cmos 10 ? 160 initial accuracy f i measured at +25 c at time of shipping ?1.5?ppm temperature stability 1,3 ? f/f o ?20 ?50 ? ? +20 +50 ppm aging f a frequency drift over pro- jected 15 year life ??10ppm powerup time 4 t osc ??10ms settling time after fs[1:0] change t frq both fs[1] and fs[0] changing simultaneously ??20ms notes: 1. see section 3. "ordering information" on page 6 for further details. 2. specified at time of order by part number. also available in frequencies from 970 to 1134 mhz and 1213 to 1417 mhz. 3. selectable parameter specified by part number. 4. time from powerup or tristate mode to f o .
si534 preliminary rev. 0.4 3 table 3. clk output levels and symmetry parameter symbol test condition min typ max units lvpecl output option 1 v o mid-level v dd ? 1.42 ? v dd ? 1.25 v v od swing (diff) 1.1 ? 1.9 v pp v se swing (single-ended) 0.5 ? 0.93 v pp lvds output option 2 v o mid-level 1.125 1.20 1.275 v v od swing (diff) 0.32 0.40 0.50 v pp cml output option 2 v o mid-level ? v dd ? 0.75 ? v v od swing (diff) 0.70 0.95 1.20 v pp cmos output option 3 v oh i oh =32ma 0.8 x v dd ? v dd v v ol i ol =32ma ? ? 0.4 rise/fall time (20/80%) t r, t f lvpecl/lvds/cml ? ? 350 ps cmos with cl = 15 pf ? 1 ? ns symmetry (duty cycle) sym lvpecl: v dd ? 1.3 v (diff) lvds: 1.25 v (diff) cmos: v dd /2 45 ? 55 % notes: 1. 50 ? to v dd ? 2.0 v. 2. r term = 100 ? (differential). 3. c l = 15 pf table 4. clk output phase jitter parameter symbol test condition min typ max units phase jitter (rms)* for f out > 500 mhz j 12 khz to 20 mhz (oc-48) 50 khz to 80 mhz (oc-192) ? ? 0.27 0.30 ? ? ps phase jitter (rms)* for f out of 125 to 500 mhz j 12 khz to 20 mhz (oc-48) ? 0.50 ? ps *note: differential modes: lvpecl/ lvds/cml. refer to an25 6 for further information. table 5. clk output period jitter parameter symbol test condition min typ max units period jitter* for f out < 160 mhz j per rms ? 1 ? ps peak-to-peak ? 5 ? *note: any output mode, incl uding cmos, lvpecl, lvds, cml. n = 1000 cycles.
si534 4 preliminary rev. 0.4 table 6. clk output phase noise (typical) configuration f c output 81.25 mhz lvds 312.5 mhz lvpecl 1066 mhz lvpecl units offest frequency (f) 100 hz 1khz 10 khz 100 khz 1mhz 10 mhz 100 mhz l (f) dbc/hz ?110 ?127 ?134 ?136 ?143 ?147 n/a ?100 ?115 ?119 ?123 ?135 ?144 ?147 ?87 ?102 ?107 ?111 ?121 ?135 ?142 table 7. absolute maximum ratings 1 parameter symbol rating units supply voltage v dd ?0.5 to +3.8 volts input voltage (any input pin) v i ?0.5 to v dd + 0.3 volts storage temperature t s ?55 to +125 oc esd sensitivity (hbm, per jesd22-a114) esd >2500 volts soldering temperature (pb-free profile) 2 t peak 260 oc soldering temperature time @ t peak (pb-free profile) 2 t p 10 seconds notes: 1. stresses beyond those listed in absolute maximum ratings may cause permanent damage to the device. functional operation or specification compliance is not implied at these conditions. 2. refer to si5xx packaging faq available for download at www.silabs.com/vcxo for further information, including soldering profiles. table 8. environmental compliance the si534 meets the following qualification test requirements. parameter conditions/ test method mechanical shock mil-std-883f, method 2002.3 b mechanical vibration mil-std-883f, method 2007.3 a solderability mil-std-8 83f, method 203.8 gross & fine leak mil-std-883f, method 1014.7 resistance to solvents mil-std-883f, method 2016
si534 preliminary rev. 0.4 5 2. pin descriptions table 9. pin descriptions pin symbol lvds/lvpecl/cml function cmos function 1 nc no connection no connection 2oe* output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 3 gnd electrical and case ground electrical and case ground 4 clk+ oscillator output oscillator output 5 clk? complementary output no connection 6v dd power supply voltage power supply voltage 7 fs[1]* frequency select msb frequency select msb 8 fs[0]* frequency select lsb frequency select lsb *note: fs[1:0] and oe include a 17 k ? pullup resistor to v dd . see section ?ordering information? for details on frequency value ordering. (top view) lvds/lvpecl/cml cmos 1 2 3 6 5 4 gnd oe v dd clk+ clk? nc fs[1] fs[0] 7 8 1 2 3 6 5 4 gnd oe v dd clk nc nc fs[1] fs[0] 7 8
si534 6 preliminary rev. 0.4 3. ordering information the si534 xo was designed to support a variety of options including fr equency, temperatur e stability, output format, and v dd . specific device configurations are programmed into the si534 at time of shipment. configurations can be specified using the part num ber configuration chart below. silicon laboratories provi des a web browser- based part number configur ation utility to simplify th is process. refer to www.silabs.com/vcxopartnumber to access this tool and for further ordering instructions. the si534 is supplied in an industry-standard, rohs compliant, 6-pad, 5 x 7 mm package. figure 1. part number convention example part number: 534ab000108bgr is a 5 x 7 mm quad xo in a 8 pad package. since the six digit code (000108) is > 000100, f0 is 644.53125 mhz (lower frequency) and f1 is 693.48299 (higher frequency), with a 3.3 v supply and lvpecl output. temperature stability is specified as 20 ppm. the part is specified for a ?40 to +85 c ambient temperature r ange operation and is shipped in tape and reel format. dd r = tape & reel blank = trays operating temp range (c) g ?40 to +85 c device revision letter 2 nd option code code temperature stability (ppm, max, ) a 50 b 20 534 quad xo product family 1 st option code code vdd output format a3.3lvpecl b3.3lvds c3.3cmos d3.3cml e2.5lvpecl f2.5lvds g2.5cmos h2.5cml j1.8cmos k1.8cml note : cmos available to 160 mhz. 6-digit frequency designator code four unique frequencies can be specified within the following bands of frequencies: 10 to 945 mhz, 970 to 1134 mhz, and 1213 to 1417 mhz. a six digit code w ill be assigned for the specified combination of frequencies. codes > 000100 refer to quad xos programmed with the lowest frequency value selected when fs[1:0] = 00, and the highest value when fs[1:0] = 11. six digit codes < 000100 refer to quad xos programmed with the highest frequency value selected when fs[1:0] = 00, and the lowest value when fs[1:0] = 11. 534 x x xxxxxx b g r
si534 preliminary rev. 0.4 7 4. outline diagram and suggested pad layout figure 2 illustrates the package details for the si534. table 10 lists the val ues for the dimensions shown in the illustration. figure 2. si534 outline diagram table 10. package diagram dimensions (mm) dimension min nom max a 1.45 1.65 1.85 b1.21.41.6 c0.60 typ d 0.97 1.17 1.37 d 7.00 bsc d1 6.10 6.2 6.30 e 2.54 bsc e 5.00 bsc e1 4.30 4.40 4.50 l 1.07 1.27 1.47 m0.81.01.2 s 1.815 bsc r 0.7 ref aaa ? ? 0.15 bbb ? ? 0.15 ccc ? ? 0.10 ddd ? ? 0.10
si534 8 preliminary rev. 0.4 5. 8-pin pcb land pattern figure 3 illustrates the 8-pin pcb land pa ttern for the si554. table 11 lists the values for the dimensions shown in the illustration. figure 3. si534 pcb land pattern table 11. pcb land pettern dimensions (mm) dimension min max d2 5.08 ref d3 5.705 ref e 2.54 bsc e2 4.20 ref gd 0.84 ? ge 2.00 ? vd 8.20 ref ve 7.30 ref x1 1.70 typ x2 1.545 typ y1 2.15 ref y2 1.3 ref zd ? 6.78 ze ? 6.30 note: 1. dimensioning and tolerancing per the ansi y14.5m-1994 specification. 2. land pattern design follows ipc-7351 guidelines. 3. all dimensions shown are at maximum material condition (mmc). 4. controlling dimension is in millimeters (mm).
si534 preliminary rev. 0.4 9 d ocument c hange l ist revision 0.3 to revision 0.4 updated 1. "electrical sp ecifications" on page 2. updated ordering and format of tables 1?9. updated lvds and cml in table 3, ?clk output levels and symmetry,? on page 3. added table 6, ?clk output phase noise (typical),? on page 4.
si534 10 preliminary rev. 0.4 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.
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